`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:25:40 10/21/2012 
// Design Name: 
// Module Name:    Minor_FSM_C 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Minor_FSM_C( clk, reset, start, speed_x, speed_y, dir_x, dir_y, ball_x, ball_y, ControlEstado
 );
	input clk, reset, start;
	input [5:0] speed_x, speed_y;
	input dir_x, dir_y; 
	output [9:0] ball_x, ball_y;
	output ControlEstado;
	reg ControlEstado;
	reg [9:0] ball_x,ball_y;	
	parameter state0 = 0;  //T1
   parameter state1 = 1;  //T2	
	reg [1:0] state;
	initial begin
               state <= state0;
					ball_x = 400;
					ball_y = 50;
					ControlEstado=0;
				end
   always@(posedge clk)
		begin
			if (reset) 
			begin
				state <= state0;
				ball_x = 400;
				ball_y = 50;
				ControlEstado=0;
			end
			if(ControlEstado)
				begin
					ControlEstado=0;
				end
			else
				case (state)
					state0 :
					begin
						if (start)
						begin
							ControlEstado=0;
							state <= state1;
						end
						else
							state <= state0;
					end				
					state1 :
					begin
							if(dir_x == 1)
								ball_x = ball_x + speed_x;
							else
								ball_x = ball_x - speed_x;
							if(dir_y == 1)
								ball_y = ball_y + speed_y;	
							else
								ball_y = ball_y - speed_y;	
							state <= state0;
							ControlEstado = 1;
					end				         
				endcase
			end
endmodule

